1. Field of the Invention
The present invention relates in general to an insulated gate field effect semiconductor device and method of manufacturing the same.
2. Description of the Prior Art
A variety of approaches have been carried out in order to miniaturize integrated circuits and achieve a higher packing density in a chip. Particularly, remarkable advances have been reported in the development of the technology to miniaturize insulated gate field effect semiconductor devices, denoted as MOSFET for short. MOS is the acronym of Metal Oxide Semiconductor. The metal used in MOSFETs generally includes, in addition to genuine metals, conductive materials such as semiconductors having a sufficient conductivity, alloys composed of semiconductor(s) and/or metal(s). The oxide generally includes, in addition to genuine oxides, insulating materials having a sufficient resistivity such as nitrides. Although these materials do exactly not correspond to the acronym MOS, the term MOSFET is used in the broad sense in this description.
The miniaturizing of MOSFETs is realized by decreasing the width of the gate electrode. The decrease of the width of the gate electrode leads to the decrease of the channel length underlying the gate electrode. This also results in a high operational speed because the short channel length decreases the time required for carriers to pass across the channel.
The miniaturizing, on the other hand, gives rise to other problems, i.e. short channel effects. One of the most serious problems thereof is hot electron effects. In the structure comprising highly doped source and drain regions with an inversely doped intervening channel region therebetween, the strength of the electric field at the boundary between the channel region and the highly doped region increases as the channel length decreases. As a result, the characteristics of the device are unstable.
The LDD (lightly-doped-drain) structure has been proposed to solve the above problem. This structure is schematically illustrated in FIG. 1(D). In the figure, reference numeral 207. designates a lightly doped region formed inside of a highly doped region 206. The region 207 is called a LDD region. By provision of such a LDD region, the strength of the electric field in the vicinity of the boundary between the channel region and the drain region is decreased so that the operation of the device becomes more stable.
FIGS. 1(A) to 1(D) are cross sectional views showing a method of making a conventional MOSFET. Although an n-channel transistor is explained here, a p-channel transistor is formed in the same manner only by inverting the conductivity type. A semiconductor film is deposited onto an insulating substrate and patterned in order to define a semiconductor active region. An oxide film and a conductive film are deposited on the semiconductor film and patterned by etching in order to form a gate electrode 201 insulated by a gate insulating film 202. With the gate electrode 201 and the insulating film 202 as a mask, lightly doped regions 203 are formed by ion implantation in a self-aligning manner.
Next, the structure is coated with an insulating film 204 such as a PSG film. The insulating film 204 is removed by an anisotropic etching (directional etching) leaving spacers 205 flanking the gate electrode 201. With the spacers 205 as a mask, heavily doped regions 206 are formed to provide source and drain regions. By employing this LDD design, the channel length can be decreased to as short as 0.1 micrometer while the channel length in usual designs can not be decreased to 0.5 micrometer or shorter.
The problems associated with the short channel designs, however, are not completely solved by this technique. Another problem is the resistance of the gate electrode which has become narrow. Even if the switching speed of the device is increased by the short channel, the speed-up may possibly come to naught due to propagation delay along the high resistant gate electrode. The resistance of the gate electrode can be decreased to some extent by employing a metal silicide having a low resistivity in place of polysilicon to form the gate electrode or by providing a low resistant line such as an aluminum line extending along the gate electrode. These techniques, however, can not solve the high resistance problem when the width of the gate electrode is no larger than 0.3 micrometer.
Another approach to solve the problem is to increase the aspect ratio of the gate electrode, i.e. the ratio of the height to the width of the gate electrode. The resistance of the gate electrode decreases in proportion to the cross sectional area which increases as the aspect ratio increases. From the view point of manufacture restraints, the aspect ratio can not be increased so much. This is mainly because the width of the spacers depend on the height of the gate electrode. The spacer is formed with its width of 20% or wider of the height of the gate electrode. Accordingly if 0.1 micrometer width L (FIG. 1(D)) is desired, the height of the gate electrode can not exceed 0.5 micrometer. If the gate electrode has a height exceeding 0.5 micrometer, the width L exceeds 0.1 micrometer resulting in a higher resistance between the source and drain regions.
In the case of 0.5 micrometer height (h), 1.0 micrometer width (W) and 0.1 micrometer width (L) in FIG. 1(D), if the width (W) of the gate electrode is desired to be decreased to 0.5 micrometer, the height of the electrode must be increase to 1.0 micrometer in order to avoid increase of the gate resistance. The width (L) of the spacers, however, becomes 0.2 micrometer so that the resistance between the source and drain regions is doubled. The halved channel length is expected to improve double the operational speed. The increase of double the source and drain resistance, however, cancels the improvement. Accordingly, the operational speed remains same as achieved before the shrinkage in size.
Usually, the width of the spacer becomes as wide as 50% to 100% of the height of the gate electrode, which width provides a further severe condition. The aspect ratios of the gate electrodes, therefore, have been no higher than 1, or in many cases no higher than 0.2 in accordance with the conventional LDD technique. In addition to this, the width of the spacer has been substantially dispersed, due to expected variations of production, which results in dispersed characteristics of the products. The conventional LDD technique has brought high integrations and high speeds and, on the contrary, impeded further improvement.
On the other hand, recently, semiconductor integrated circuits have been formed within semiconductor thin films deposited on insulating substrates such as glass substrates (e.g., in the case of liquid crystal displays and image sensors) or on single crystal semiconductor substrates coated with insulating films (e.g., in the case of three-dimensional ICs). The LDD technique is often effective also in these cases. Because of disparity of thickness of one PSG film formed over a large glass substrate, the sizes of spacers become different depending upon the positions of the substrate.
In the case or LDD designs to be formed on an insulating surface for three-dimensional ICs, if there have been formed other circuits under the surface, the surface is usually not even so that the sizes of spacers are substantially dispersed. The yield of the conventional productions of three-dimensional ICs has therefore been low with dispersed characteristics.